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(R)
SP3249E
Intelligent +3.0V to +5.5V RS-232 Transceivers
s Meets true EIA/TIA-232-F Standards from a +3.0V to +5.5V power supply s Interoperable with EIA/TIA-232 and adheres to EIA/TIA-562 down to a +2.7V power source s Minimum 250Kbps data rate under load s Regulated Charge Pump Yields Stable RS-232 Outputs Regardless of VCC Variations s Enhanced ESD Specifications: +15KV Human Body Model +15KV IEC1000-4-2 Air Discharge +8KV IEC1000-4-2 Contact Discharge DESCRIPTION The SP3249E device is an RS-232 transceiver solution intended for portable or hand-held applications such as notebook and palmtop computers. The SP3249E uses an internal high-efficiency, charge-pump power supply that requires only 0.1F capacitors in 3.3V operation. This charge pump and Sipex's driver architecture allow the SP3249E device to deliver compliant RS-232 performance from a single power supply ranging from +3.0V to +5.0V. The SP3249E is a 5-driver/3-receiver device, ideal for laptop/notebook computer and PDA applications.
SELECTION TABLE
Part Number Power Supplies RS-232 Drivers RS-232 Receivers External Components AUTO ON-LINETM Circuitry TTL 3-State Number of Pins
SP3223E SP3243E SP3238E SP3239E SP3249E
+3.0V to +5.5V +3.0V to +5.5V +3.0V to +5.5V +3.0V to +5.5V +3.0V to +5.5V
2 3 5 5 5
2 5 3 3 3
4 capacitors 4 capacitors 4 capacitors 4 capacitors 4 capacitors
YES YES YES NO NO
YES YES YES YES NO
20 28 28 28 24
Applicable U.S. Patents - 5,306,954; and other patents pending.
Rev.4/08/02 SP3249E Intelligent +3.0V to +5.5V RS-232 Transceivers (c) Copyright 2002 Sipex Corporation
1
ABSOLUTE MAXIMUM RATINGS
These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability and cause permanent damage to the device. VCC.......................................................-0.3V to +6.0V V+ (NOTE 1).......................................-0.3V to +7.0V V- (NOTE 1)........................................+0.3V to -7.0V V+ + |V-| (NOTE 1)...........................................+13V ICC (DC VCC or GND current).........................+100mA
Input Voltages TxIN ...................................................-0.3V to +6.0V RxIN...................................................................+25V Output Voltages TxOUT.............................................................+13.2V RxOUT,......................................-0.3V to (VCC + 0.3V) Short-Circuit Duration TxOUT.....................................................Continuous Storage Temperature......................-65C to +150C
Note 1: V+ and V- can have maximum magnitudes of 7V, but their absolute difference cannot exceed 13V.
SPECIFICATIONS
VCC = +3.0 to +5.5, C1 -C4 = 0.1F (tested at 3.3V + 5%), C1-C4 = 0.22F (tested at 3.3V + 10%), C1 = 0.047F, and C2-C4 = 0.33F (tested at 5.0V + 10%), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Supply Current
MIN.
TYP. 0.3
MAX. 1.0
UNITS mA
CONDITIONS VCC, no load
LOGIC INPUTS AND RECEIVER OUTPUTS Input Logic Threshold LOW HIGH Input Leakage Current Output Voltage LOW Output Voltage HIGH DRIVER OUTPUTS Output Voltage Swing Output Resistance Output Short-Circuit Current RECEIVER INPUTS Input Voltage Range Input Threshold LOW Input Threshold LOW Input Threshold HIGH Input Threshold HIGH Input Hysteresis Input Resistance 3 -25 0.6 0.8 1.2 1.5 1.5 1.8 0.5 5 7 2.4 2.4 25 V V V V V V k VCC = 3.3V VCC = 5.0V VCC = 3.3V VCC = 5.0V 5.0 300 35 60 5.4 V mA All driver outputs loaded with 3K to GND VCC = V+ = V- = 0V, VOUT = 2V VOUT = GND VCC - 0.6 VCC - 0.1 0.8 2.4 0.01 1.0 0.4 V V A V V VCC = +3.3V or +5.0V, TxIN VCC = +3.3V or +5.0V, TxIN TxIN, TA = 25C IOUT = 1.6mA IOUT = -1.0mA
Rev.4/08/02
SP3249E Intelligent +3.0V to +5.5V RS-232 Transceivers
(c) Copyright 2002 Sipex Corporation
2
SPECIFICATIONS
VCC = +3.0 to +5.5, C1 -C4 = 0.1F (tested at 3.3V + 5%), C1-C4 = 0.22F (tested at 3.3V + 10%), C1 = 0.047F, and C2-C4 = 0.33F (tested at 5.0V + 10%), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER TIMING CHARACTERISTICS Maximum Data Rate Receiver Propagation Delay tPHL tPLH Receiver Output Enable Time Receiver Output Disable Time Driver Skew Receiver Skew Transition-Region Slew Rate
MIN.
TYP.
MAX.
UNITS
CONDITIONS
250
kbps
RL = 3k, CL = 1000pF, one driver switching Receiver input to receiver output, CL = 150pF Receiver input to receiver output, CL = 150pF Normal operation Normal operation I tPLH - tPLH I,TA = 25C I tPLH - tPLH I VCC = 3.3V, RL = 3k, TAMB =25C, measurements taken from -3.0V to +3.0V or +3.0V to -3.0V
0.15 0.15 200 200 100 50 30
s s ns ns ns ns V/s
TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise noted, the following performance characteristics apply for VCC = +3.3V, 250kbps data rate, all drivers loaded with 3k, 0.1F charge pump capacitors, and TAMB = +25C.
TRANSMITTER OUTPUT vs. LOAD CAPACITANCE
6 4 2 0 -2 0 -4 -6 pF 1000 2000 3000 4000 5000 VOH VOL
25 20 15 10 5 0 0 1000 2000 pF 3000 4000 5000 POS. SR NEG SR
SLEW RATE vs. LOAD CAPACITANCE
Figure 1. Transmitter Output vs. Load Capacitance
SUPPLY CURRENT vs LOAD CAPACITANCE
60 50 40 30 20 10 0 0 1000 2000 pF 3000 4000 5000 250Kbps 120Kbps 20Kbps
Figure 2. Slew Rate vs. Load Capacitance
Figure 3. Supply Current vs. Load Capacitance when Transmitting Data
Rev.4/08/02
SP3249E Intelligent +3.0V to +5.5V RS-232 Transceivers
(c) Copyright 2002 Sipex Corporation
3
PIN DESCRIPTION
NAME C2+ GND C2VT1OUT T2OUT T3OUT R1IN R2IN T4OUT R3IN T5OUT T5IN R3OUT T4IN R2OUT R1OUT T3IN T2IN T1IN C1VCC V+ C1+ FUNCTION Positive terminal of the inverting charge-pump capacitor. Ground. Negative terminal of the inverting charge-pump capacitor. Regulated -5.5V output generated by the charge pump. RS-232 driver output. RS-232 driver output. RS-232 driver output. RS-232 receiver input. RS-232 receiver input. RS-232 driver output. RS-232 receiver input. RS-232 driver output. TTL/CMOS driver input. TTL/CMOS receiver output. TTL/CMOS driver input. TTL/CMOS receiver output. TTL/CMOS receiver output. TTL/CMOS driver input. TTL/CMOS driver input. TTL/CMOS driver input. Negative terminal of the voltage doubler charge-pump capacitor. +3.0V to +5.5V supply voltage. Regulated +5.5V output generated by the charge pump. Positive terminal of the voltage doubler charge-pump capacitor. PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Table 1. Device Pin Description
Rev.4/08/02
SP3249E Intelligent +3.0V to +5.5V RS-232 Transceivers
(c) Copyright 2002 Sipex Corporation
4
C2+ 1 GND 2 C2- 3 V- 4 T1OUT 5 T2OUT 6 T3OUT 7 R1IN 8 R2IN 9 T4OUT 10 R3IN 11 T5OUT 12 SP3249E
24 C1+ 23 V+ 22 VCC 21 C120 T1IN 19 T2IN 18 T3IN 17 R1OUT
16 R2OUT 15 T4IN 14 R3OUT 13 T5IN
Figure 4. SP3249E Pinout Configuration
C5
+
VCC 0.1F 24 C1+ 0.1F 21 C11 C2+ 22 VCC V+ 23 C3 + 0.1F
C1
+
SP3249E
C2
+
V-
4 C4 + 0.1F
0.1F
3 C220 T1IN 19 T2IN
T1OUT 5 T2OUT 6 T3OUT 7 T4OUT 10 T5OUT 12 R1IN
TTL/CMOS INPUTS
18 T3IN 15 T4IN 13 T5IN 17 R1OUT
RS-232 OUTPUTS
8 9 11 RS-232 INPUTS
TTL/CMOS OUTPUTS
5k 16 R2OUT 5k 14 R3OUT 5k
R3IN R2IN
GND 2
Figure 5. SP3249E Typical Operating Circuit
Rev.4/08/02 SP3249E Intelligent +3.0V to +5.5V RS-232 Transceivers (c) Copyright 2002 Sipex Corporation
5
DESCRIPTION The SP3249E device meets the EIA/TIA-232 and ITU-T V.28/V.24 communication protocols and can be implemented in battery-powered, portable, or hand-held applications such as notebook or palmtop computers. The SP3249E device features Sipex's proprietary and patented (U.S. #5,306,954) on-board charge pump circuitry that generates 5.5V RS-232 voltage levels from a single +3.0V to +5.5V power supply. The SP3249E device can operate at a data rate of 250kbps fully loaded. The SP3249E is a 5-driver/3-receiver device, ideal for portable or hand-held applications. The SP3249E device is an ideal choice for power sensitive designs. THEORY OF OPERATION The SP3249E device is made up of three basic circuit blocks: 1. Drivers, 2. Receivers, and 3. the Sipex proprietary charge pump. Drivers The drivers are inverting level transmitters that convert TTL or CMOS logic levels to 5.0V EIA/ TIA-232 levels with an inverted sense relative to the input logic levels. Typically, the RS-232
VCC + 0.1F 24 C1+ 0.1F 21 C11 C2+ C2 + 0.1F 3 C220 T1IN 19 T2IN 18 T3IN 15 T4IN 13 T5IN 17 R1OUT 5k 16 R2OUT 5k 14 R3OUT 5k GND 2
T1OUT 5 T2OUT 6 T3OUT 7 T4OUT 10 T5OUT 12 R1IN 8 R2IN
output voltage swing is +5.4V with no load and +5V minimum fully loaded. The driver outputs are protected against infinite short-circuits to ground without degradation in reliability. These drivers comply with the EIA-TIA-232F and all previous RS-232 versions. Unused driver inputs should be connected to GND or VCC. The drivers can guarantee a data rate of 250kbps fully loaded with 3k in parallel with 1000pF, ensuring compatibility with PC-to-PC communication software. The slew rate of the driver output is internally limited to a maximum of 30V/s in order to meet the EIA standards (EIA RS-232D 2.1.7, Paragraph 5). The transition of the loaded output from HIGH to LOW also meets the monotonicity requirements of the standard. Figure 7 shows a loopback test circuit used to test the RS-232 Drivers. Figure 8 shows the test results of the loopback circuit with all five drivers active at 120kbps with typical RS-232 loads in parallel with 1000pF capacitors. Figure 6 shows the test results where one driver was active at 250kbps and all five drivers loaded with an RS232 receiver in parallel with a 1000pF capacitor. A solid RS-232 data transmission rate of 120kbps provides compatibility with many designs in personal computer peripherals and LAN applications. Receivers
22 VCC V+ 23 C3 + 0.1F
C5
C1
+
SP3249E
V- 4 C4 + 0.1F
RxD CTS DSR DCD RI TxD RTS DTR
The receivers convert 5.0V EIA/TIA-232 levels to TTL or CMOS logic output levels. Since receiver input is usually from a transmission line where long cable lengths and system interference can degrade the signal, the inputs have a typical hysteresis margin of 500mV. This ensures that the receiver is virtually immune to noisy transmission lines. Should an input be left unconnected, an internal 5k pulldown resistor to ground will commit the output of the receiver to a HIGH state.
RS-232 OUTPUTS
UART or Serial C
9
RS-232 INPUTS
R3IN 11
Figure 6. Interface Circuitry Controlled by Microprocessor Supervisory Circuit
Rev.4/08/02
SP3249E Intelligent +3.0V to +5.5V RS-232 Transceivers
(c) Copyright 2002 Sipex Corporation
6
Charge Pump The charge pump is a Sipex-patented design (U.S. #5,306,954) and uses a unique approach compared to older less-efficient designs. The charge pump still requires four external capacitors, but uses a four-phase voltage shifting technique to attain symmetrical 5.5V power supplies. The internal power supply consists of a regulated dual charge pump that provides output voltages 5.5V regardless of the input voltage (VCC) over the +3.0V to +5.5V range. This is important to maintain compliant RS-232 levels regardless of power supply fluctuations. The charge pump operates in a discontinuous mode using an internal oscillator. If the output voltages are less than a magnitude of 5.5V, the charge pump is enabled. If the output voltages exceed a magnitude of 5.5V, the charge pump is disabled. This oscillator controls the four phases of the voltage shifting (Figure 13). A description of each phase follows. Phase 1 (Figure 11) -- VSS charge storage -- During this phase of the clock cycle, the positive side of capacitors C1 and C2 are initially charged to VCC. Cl+ is then switched to GND and the charge in C1- is transferred to C2-. Since C2+ is connected to VCC, the voltage potential across capacitor C2 is now 2 times VCC.
VCC +
C5
0.1F C1+ 0.1F C1C2+
VCC V+ C3 + 0.1F
C1
+
SP3249E
C2
+
VC4 + 0.1F
0.1F C2-
LOGIC INPUTS LOGIC OUTPUTS
TxIN
TxOUT 1000pF
RxOUT 5k
RxIN
GND
Figure 7. Loopback Test Circuit for RS-232 Driver Data Transmission Rates
Phase 2 (Figure 12) -- VSS transfer -- Phase two of the clock connects the negative terminal of C2 to the VSS storage capacitor and the positive terminal of C2 to GND. This transfers a negative generated voltage to C 3 . This generated voltage is regulated to a minimum voltage of -5.5V. Simultaneous with the transfer of the voltage to C3, the positive side of capacitor C1 is switched to VCC and the negative side is connected to GND. Phase 3 (Figure 14)
Figure 8. Loopback Test Circuit Result at 120kbps (All Drivers Fully Loaded)
Figure 9. Loopback Test Circuit result at 250kbps (All Drivers Fully Loaded)
Rev.4/08/02
SP3249E Intelligent +3.0V to +5.5V RS-232 Transceivers
(c) Copyright 2002 Sipex Corporation
7
-- VDD charge storage -- The third phase of the clock is identical to the first phase -- the charge transferred in C1 produces -VCC in the negative terminal of C1, which is applied to the negative side of capacitor C2. Since C2+ is at VCC, the voltage potential across C2 is 2 times VCC. Phase 4 (Figure 15) -- VDD transfer -- The fourth phase of the clock connects the negative terminal of C2 to GND, and transfers this positive generated voltage across C2 to C4, the VDD storage capacitor. This voltage is regulated to +5.5V. At this voltage, the internal oscillator is disabled. Simultaneous with the transfer of the voltage to C4, the positive side of capacitor C1 is switched to VCC and the negative side is connected to GND,
allowing the charge pump cycle to begin again. The charge pump cycle will continue as long as the operational conditions for the internal oscillator are present. Since both V+ and V- are separately generated from VCC, in a no-load condition V+ and V- will be symmetrical. Older charge pump approaches that generate V- from V+ will show a decrease in the magnitude of V- compared to V+ due to the inherent inefficiencies in the design. The clock rate for the charge pump typically operates at 500kHz. The external capacitors can be as low as 0.1F with a 16V breakdown voltage rating.
VCC = +5V
+5V C1
+ -
C4
+ - +
C2
+ - -
VDD Storage Capacitor VSS Storage Capacitor
-5V
-5V
C3
Figure 10. Charge Pump -- Phase 1
VCC = +5V
C4
+ - +
C1
+ -
C2
+ - -
VDD Storage Capacitor VSS Storage Capacitor
-10V
C3
Figure 11. Charge Pump -- Phase 2
[
T
] +6V
a) C2+
1 2 2
T
0V 0V
b) C2T -6V Ch1 2.00V Ch2 2.00V M 1.00s Ch1 1.96V
Figure 12. Charge Pump Waveforms
Rev.4/08/02 SP3249E Intelligent +3.0V to +5.5V RS-232 Transceivers (c) Copyright 2002 Sipex Corporation
8
VCC = +5V
+5V C1
+ -
C4
+ - +
C2
+ - -
VDD Storage Capacitor VSS Storage Capacitor
-5V
-5V
C3
Figure 13. Charge Pump -- Phase 3
VCC = +5V
+10V C1
+ -
C4
+ - +
C2
+ - -
VDD Storage Capacitor VSS Storage Capacitor
C3
Figure 14. Charge Pump -- Phase 4
VCC
C5
+
0.1F
24
C1 + C1+ 0.1F
22 VCC
21 C11
C2+
C2-
V+
23
C3
+
0.1F
+ C2 0.1F
SP3249E
V-
3
4
C4 0.1F
17 R1OUT 5k 16 R2OUT 5k 14 R3OUT 5k 20 T1IN 19 T2IN 18 T3IN 15 T4IN 13 T5IN
R1IN R2IN R3IN
8 9 11
+
T1OUT T2OUT T3OUT T4OUT T5OUT
5 6 7 10 12
DB-9 Connector 6 7 8 9 1 2 3 4 5
GND 2
DB-9 Connector Pins: 1. Received Line Signal Detector 2. Received Data 3. Transmitted Data 4. Data Terminal Ready 5. Signal Ground (Common) 6. 7. 8. 9. DCE Ready Request to Send Clear to Send Ring Indicator
Figure 15. Circuit for the connectivity of the SP3249E with a DB-9 connector
Rev.4/08/02 SP3249E Intelligent +3.0V to +5.5V RS-232 Transceivers (c) Copyright 2002 Sipex Corporation
9
ESD TOLERANCE The SP3249E device incorporates ruggedized ESD cells on all driver output and receiver input pins. The ESD structure is improved over our previous family for more rugged applications and environments sensitive to electrostatic discharges and associated transients. The improved ESD tolerance is at least +15kV without damage nor latch-up. There are different methods of ESD testing applied:
a) MIL-STD-883, Method 3015.7 b) IEC1000-4-2 Air-Discharge c) IEC1000-4-2 Direct Contact
normal usage. The transceiver IC receives most of the ESD current when the ESD source is applied to the connector pins. The test circuit for IEC1000-4-2 is shown on Figure 20. There are two methods within IEC1000-4-2, the Air Discharge method and the Contact Discharge method. With the Air Discharge Method, an ESD voltage is applied to the equipment under test (EUT) through air. This simulates an electrically charged person ready to connect a cable onto the rear of the system only to find an unpleasant zap just before the person touches the back panel. The high energy potential on the person discharges through an arcing path to the rear panel of the system before he or she even touches the system. This energy, whether discharged directly or through air, is predominantly a function of the discharge current rather than the discharge voltage. Variables with an air discharge such as approach speed of the object carrying the ESD potential to the system and humidity will tend to change the discharge current. For example, the rise time of the discharge current varies with the approach speed. The Contact Discharge Method applies the ESD current directly to the EUT. This method was devised to reduce the unpredictability of the ESD arc. The discharge current rise time is constant since the energy is directly transferred without the air-gap arc. In situations such as hand held systems, the ESD charge can be directly discharged to the equipment from a person already holding the equipment. The current is transferred on to the keypad or the serial port of the equipment directly and then travels through the PCB and finally to the IC.
RS S
The Human Body Model has been the generally accepted ESD testing method for semiconductors. This method is also specified in MIL-STD-883, Method 3015.7 for ESD testing. The premise of this ESD test is to simulate the human body's potential to store electro-static energy and discharge it to an integrated circuit. The simulation is performed by using a test model as shown in Figure 16. This method will test the IC's capability to withstand an ESD transient during normal handling such as in manufacturing areas where the ICs tend to be handled frequently. The IEC-1000-4-2, formerly IEC801-2, is generally used for testing ESD on equipment and systems. For system manufacturers, they must guarantee a certain amount of ESD protection since the system itself is exposed to the outside environment and human presence. The premise with IEC1000-4-2 is that the system is required to withstand an amount of static electricity when ESD is applied to points and surfaces of the equipment that are accessible to personnel during
RC C SW1 SW1
DC Power Source
SW2 SW2 CS S
Device Under Test
Figure 16. ESD Test Circuit for Human Body Model
Rev.4/08/02 SP3249E Intelligent +3.0V to +5.5V RS-232 Transceivers (c) Copyright 2002 Sipex Corporation
10
Contact-Discharge Module
RC C SW1
DC Power Source
RS S
RV SW2
CS S
Device Under Test
RS and RV add up to 330 for IEC1000-4-2.
Figure 17. ESD Test Circuit for IEC1000-4-2
The circuit model in Figures 16 and 17 represent the typical ESD testing circuit used for all three methods. The CS is initially charged with the DC power supply when the first switch (SW1) is on. Now that the capacitor is charged, the second switch (SW2) is on while SW1 switches off. The voltage stored in the capacitor is then applied through RS, the current limiting resistor, onto the device under test (DUT). In ESD tests, the SW2 switch is pulsed so that the device under test receives a duration of voltage. For the Human Body Model, the current limiting resistor (RS) and the source capacitor (CS) are 1.5kW an 100pF, respectively. For IEC-1000-42, the current limiting resistor (RS) and the source capacitor (CS) are 330W an 150pF, respectively. The higher CS value and lower RS value in the IEC1000-4-2 model are more stringent than the Human Body Model. The larger storage capacitor injects a higher voltage to the test point when SW2 is switched on. The lower current limiting resistor increases the current charge onto the test point. DEVICE PIN TESTED
Driver Outputs Receiver Inputs
30A
15A
0A t=0ns t Figure 18. ESD Test Waveform for IEC1000-4-2 t=30ns
HUMAN BODY MODEL
15kV 15kV
i
Air Discharge
15kV 15kV
IEC1000-4-2 Direct Contact
8kV 8kV
Level
4 4
Table 2. Transceiver ESD Tolerance Levels
Rev.4/08/02
SP3249E Intelligent +3.0V to +5.5V RS-232 Transceivers
(c) Copyright 2002 Sipex Corporation
11
PACKAGE: PLASTIC SHRINK SMALL OUTLINE (SSOP)
E H
D A O e B A1 L
DIMENSIONS (Inches) Minimum/Maximum (mm) A A1 B D E e H L O
24-PIN 0.068/0.078 (1.73/1.99) 0.002/0.008 (0.05/0.21) 0.010/0.015 (0.25/0.38) 0.317/0.328 (8.07/8.33) 0.205/0.212 (5.20/5.38) 0.0256 BSC (0.65 BSC) 0.301/0.311 (7.65/7.90) 0.022/0.037 (0.55/0.95) 0/8 (0/8)
Rev.4/08/02
SP3249E Intelligent +3.0V to +5.5V RS-232 Transceivers
(c) Copyright 2002 Sipex Corporation
12
PACKAGE: PLASTIC THIN SMALL OUTLINE (TSSOP)
e
0.126 BSC (3.2 BSC) 0.252 BSC (6.4 BSC) 1.0 OIA 0.169 (4.30) 0.177 (4.50)
DIMENSIONS in inches (mm) Minimum/Maximum Symbol D e 24 Lead 0.303/0.311 (7.70/7.90) 0.026 BSC (0.65 BSC)
0.039 (1.0)
0'-8' 12'REF e/2 0.039 (1.0) 0.043 (1.10) Max D 0.033 (0.85) 0.037 (0.95)
0.007 (0.19) 0.012 (0.30)
0.002 (0.05) 0.006 (0.15) (2) 0.008 (0.20)
0.004 (0.09) Min
0.004 (0.09) Min Gage Plane
0.010 (0.25)
(3) 1.0 REF
0.020 (0.50) 0.026 (0.75)
(1)
Rev.4/08/02
SP3249E Intelligent +3.0V to +5.5V RS-232 Transceivers
(c) Copyright 2002 Sipex Corporation
13
ORDERING INFORMATION

Model SP3249ECA SP3249ECY SP3249EEA SP3249EEY
Temperature Range 0C to +70C 0C to +70C
Package Types 24-pin SSOP 24-pin TSSOP 24-pin SSOP 24 -pin TSSOP

Please consult the factory for pricing and availability on a Tape-On-Reel option.
Corporation
SIGNAL PROCESSING EXCELLENCE
Sipex Corporation Headquarters and Sales Office 22 Linnell Circle Billerica, MA 01821 TEL: (978) 667-8700 FAX: (978) 670-9001 e-mail: sales@sipex.com Sales Office 233 South Hillview Drive Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600
Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.
Rev.4/08/02
SP3249E Intelligent +3.0V to +5.5V RS-232 Transceivers
14
-40C to +85C -40C to +85C

(c) Copyright 2002 Sipex Corporation

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